1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device, and more specifically, it relates to a nonvolatile semiconductor memory device storing data of at least two bits in a single memory cell.
2. Description of the Background Art
The capacity of a flash memory is increased by a refinement technique or a multilevel storage technique. The importance of the multilevel storage technique for storing data of at least two bits in a single memory cell is conceivably increased in the future as the storage capacity is increased.
A multilevel storage flash memory storing data of two bits in a single memory cell supplies a read voltage to a word line a plurality of times in order to read data from a memory cell, and supplies a write voltage a plurality of times for writing data in the memory cell. Therefore, this type of flash memory requires a longer time for first access or writing as compared with a flash memory storing data of one bit in a single memory cell.
"A 256 MB Multilevel Flash Memory with 2 MB/s Program Rate for Mass Storage Applications" by Nozoe et al., ISSCC 1999, Digest of Technical Papers, pp. 110 to 111 discloses a quadrilevel flash memory storing data of two bits in a single memory cell. Each memory cell selectively holds four types of levels for storing data of two bits. This flash memory includes a word decoder selectively applying a voltage of 2.4 V, 3.2 V or 4.0 V to a word line, a sense latch circuit arranged at the center of a memory cell array and connected with a pair of bit lines provided on both sides, an upper data latch circuit arranged on one side of the memory cell array and connected with the pair of bit lines, and a lower data latch circuit arranged on another side of the memory cell array and connected with the pair of bit lines. The voltage of 2.4 V is applied to the word line, and data thereby read on the pair of bit lines is first latched by the sense latch circuit, and then transferred to the upper data latch circuit through the pair of bit lines. The voltage of 3.2 V is applied to the word line, and data thereby read on the pair of bit lines is first latched by the sense latch circuit, and then transferred to the lower data latch circuit through the pair of bit lines. The voltage of 4.0 is applied to the word line, and data thereby read on the pair of bit lines is latched by the sense latch circuit. Then, the exclusive OR of the data latched by the sense latch circuit and the data latched by the upper data latch circuit is operated and the result rewritten back in the upper data latch circuit. Finally, the data latched by the upper data latch circuit and the lower data latch circuit are output as read data of two bits.
The aforementioned flash memory transfers the data through the pair of bit lines and employs the pair of bit lines for operating the exclusive OR, and hence the read time is lengthened to disadvantageously increase power consumption. Further, it is difficult to expand such a quadrilevel flash memory storing data of two bits in a single memory cell to an octalevel flash memory storing data of three bits in a single memory cell or a 16-level flash memory storing data of four bits in a single memory cell.